1. Field of the Invention
The present invention relates to techniques for automatic execution of operations of multiplication, i.e., to techniques for generating, starting from at least one first binary digital signal and one second binary digital signal representing respective factors to be multiplied together, an output signal representing the product of these factors.
The invention has been developed with particular attention paid to its possible application to the multiplication of floating-point real numbers, with a view to its use in devices such as, for example, low-power-consumption electronic devices, in particular portable wireless devices.
2. Description of the Related Art
The arithmetic logic units (ALUs) of electronic devices traditionally comprise multiplication units for floating-point numbers. These are typically circuits which, starting from a first binary digital signal and a second binary digital signal representing respective factors to be multiplied, expressed in floating-point format, generate an output signal, which is also expressed in floating-point format and represents the product of the factors multiplied together.
For reasons of clarity and simplicity of illustration, in the remainder of the present description, both in discussing the solutions of the known art and in presenting possible embodiments of the invention, exclusive reference will be made to the multiplication of two factors. What has been said with reference to the multiplication of two factors extends, however, also to multiplications involving more factors.
In the framework of units for floating-point multiplication, by far the most widely used representation is the one envisaged by the standard IEEE754. According to this standard, real numbers are expressed via a binary representation of the fractional part or mantissa and of the exponent in powers of a base 2, according to the general formula:
                                                        f              =                                                ∑                                      i                    =                                          -                      K                                                        K                                ⁢                                                      a                    i                                    ·                                      2                    i                                                                                                                                                                                                                                              a                i                            ∈                              {                                  0                  ,                  1                                }                                                                        (        1        )            where f is the real number to be represented, and K is the number of bits available for the representation.
A number represented in the floating-point form comprises three basic components: sign SGN, exponent E, and mantissa M.
According to the IEEE754 standard, it is possible to adopt a representation in single precision of the real number f, using: a number NS, equal to one, of sign bits SGN; a number NE, equal to 8, of exponent bits E; and a number NM equal to 23, of mantissa bits M.
Alternatively, it is possible to adopt a double-precision representation, where NS has the value 1, NE has the value 11, and NM has the value 52.
In this way, the mantissa M and the exponent E are represented by means of two respective integer values.
The sign bit SGN is always just one and assumes the value “0” to indicate a positive number, and the value “1” to indicate a negative number.
For the exponent E there is adopted a representation that envisages adding a fixed value, referred to as “bias”, to a base exponent exp. For example, if the base exponent has the value 73 and the bias value is 127, the encoded exponent E has the value 200.
The bias value is fixed and assumes the value 127 in single precision and the value 1023 in double precision. The adoption of the fixed bias value means that the lowest number will be represented in the exponent by a series of zeroes in binary form, whilst the highest one will be represented by a series of ones.
According to the IEEE754 standard, there is moreover adopted a so-called normalized representation of the real number f according to the formula:f=(−1 )SGN*(1.0+M)*2(E-bias)  (2)
The convention on normalized numbers envisages, that is, that the first bit upstream of the point will always have the value one, and all the bits downstream of the point will be used for representing the mantissa M and will increase the precision.
Summing up, the rules for encoding a real number according to the IEEE754 standard are the following:                the sign bit SGN has the value “0” for indicating a positive number and “1” for indicating a negative number;        the base of the exponent E is 2;        the field of the exponent E is obtained by adding the value of the exponent exp to a fixed bias value; and        the first bit of the mantissa M is always one and hence is not represented explicitly.        
The IEEE754 standard moreover adopts a representation, termed “denormalized representation”, when the real number f has exponent zero and mantissa other than zero. This notation is used for representing the real numbers very close to zero.f=(−1)SGN*0.M*2(-bias−1)  (3)
In this case, that is, there is not, hence, a one set before the mantissa M.
In brief, the IEEE754 standard envisages the use of two encodings:                a denormalized encoding for numbers very close to zero; and        a normalized encoding in all the other cases.        
This double representation calls for adding the bias in the exponent in order to distinguish the two cases (denormalized if EXP=0)
1.xxxxx . . . x normalized form; and
0.xxxxx . . . x denormalized form,
which, under due analysis, represents the weak point in the perspective of a low power-consumption multiplier device.
The reason for this is that, in the denormalized case, there does not exist the guarantee that the product of the mantissas is made between two “big” numbers.
It will moreover be appreciated that the term “normalized” is applied because the real number with the most significant bit is normalized to one.
With the above rules, by encoding the real number f using a sign bit NS, a number NM of bits for the mantissa and a number NE of bits for the field of the exponent, we obtain, for example, as regards the range of variation, a maximum positive value Nmax:
                    NMax        =                              ∑                          i              =              0                        NM                    ⁢                                    2                              -                i                                      ·                          2              bias                                                          (        4        )            
Other characteristics of the encoding according to the IEEE754 standard regard the zeroes, which is not represented in normalized form, on account of the presence of the one as first mantissa bit. The zero is expressed with a special value with a field of the exponent zero and mantissa zero.
The IEEE754 standard moreover envisages specific encodings to indicate infinite values, indeterminate values and errors (NaN codes).
In order to make a multiplication between floating-point numbers defined in mantissa M and exponent E according to the encoding envisaged by the IEEE754 standard, there is hence necessary an operation of addition on the exponents of the operands, whilst there is required an operation of product for their mantissas.
The multiplication between real numbers expressed according to the IEEE754 standard, in particular with reference to the number of bits necessary for the exponent and mantissa, hence requires—for a “canonical” embodiment—the use of arithmetic logic units with characteristics of complexity and power absorption that are far from compatible with the conditions of use typical of portable electronic devices, such as mobile phones and PDAs.
In order to deal with the problem, a possible solution could be a reduction of the number of bits used for representing the exponent and, in particular, for representing the mantissa. This approach would lead, however, to an undesirable loss of precision in obtaining the result.
It is moreover necessary to consider the fact that, for the calculation of floating-point products, there are normally used integer multiplier circuits, such as partial-sum multiplier circuits. These multiplier circuits are based upon the calculation of the partial sums of partial products calculated by a logic circuit based upon a matrix, such as the one represented in FIG. 1.
In the specific case of 4-bit integers, such a matrix logic circuit consists of a matrix of AND logic gates, which receives on the rows the bits A0 . . . A3 of the mantissa of an operand and on the columns the bits B0 . . . B3 of the mantissa of the other operand, supplying addenda of partial products P1 . . . P16, corresponding to the product of bits A3B0 . . . A0B3, ordered according to rows and columns. Subsequently, there are performed partial sums of the partial sums on the rows of the matrix, on the columns or else on the diagonal.
In this case, the area occupied by the circuit and its power consumption depend basically upon the number of the rows or of the columns that it requires.
Alternatively, in multiplication units there is also used the so-called Booth algorithm for multiplication.
An integer Y can be expressed as a sum of powers of a base 2 with coefficients yi:Y=y02m+y12m-1+y22m-2+ . . . +ym-12+ym  (5)
It hence follows that a product U between a multiplicand number X and the integer Y can be expressed as:
                    U        =                  XY          =                                    ∑                              i                =                0                            m                        ⁢                                          (                                                      y                                          i                      +                      1                                                        -                                      y                    i                                                  )                            ·              X              ·                              2                                  m                  -                  i                                                                                        (        6        )            
A multiplication can hence be made by getting the arithmetic logic unit to perform repeated operations of addition and shift on the multiplicand X, as indicated in Table 1 appearing below, which represents the rules of the so-called Booth algorithm 1:
TABLE 1Yi+1yiArithmetic operation00001−X  10X110
The adoption of the Booth algorithm, albeit advantageous in so far as it leads to a sensible increase in the processing speed, does not lead to an economy in terms of power absorbed by the circuits and in terms of area occupied thereby.